• Sr ASIC FPGA Engineer

    Posted Date 4 months ago(5/29/2019 11:50 AM)
    ID
    2019-38341
    Job Location
    USA-MN-Bloomington
    Required Clearance
    Secret
    Category
    Engineering-Hardware
    Employment Type
    Full Time
    Hiring Company
    General Dynamics Mission Systems
  • Basic Qualifications

    Bachelor's degree in Electrical or Computer Engineering, a related specialized area or field is required (or equivalent experience) plus a minimum of 2 years of relevant experience; or Master's degree.

     

    CLEARANCE REQUIREMENTS:
    Department of Defense secret security clearance is not required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

    Responsibilities for this Position

    A Relocation package may be available for this position.

     

    General Dynamics Mission Systems has an immediate opening for a Senior ASIC FPGA Engineer.  This position provides an opportunity to further advance the cutting-edge technology that supports some of our nation’s core defense/intelligence services and systems.  General Dynamics Mission Systems employees work closely with esteemed customers to develop solutions that allow them to carry out high-stakes national security missions.

     

    REPRESENTATIVE DUTIES AND TASKS:

    Seeking an experienced FPGA Verification Engineer who possess functional verification experience utilizing Object Orientated programming (C, C#, C+), familiarity with Universal Verification Methodologies (UVM), System Verilog, assertions checking and constrained random stimulus. 

    SUCCESSFULL FPGA VERIFICATION CANDIDATE ATTRIBUTES:

    • Has significant experience writing object orientated programming code such as C, C#, C+
    • Contributed to verification plans, UVM testbenches, System Verilog assertions, and functional coverage models to support coverage-driven verification
    • Has experience with functional verification methodologies to meet functional and code coverage goals
    • Constrained random behavioral and register transfer level (RTL) simulations
    • Has experience with Mentor QuestaSim and Mentor Graphics Verification IP
    • Familiar with Verilog/System Verilog
    • Familiar with requirement decomposition
    • Basic understanding of Hardware Logic Types
    • Basic understanding of Computer Architecture
    • Direct Programming Interface (DPI) experience
    • Linux, Jenkins and various other scripting approaches
    • Familiar with PCIe, Gigabit Ethernet, Fibre Channel, AXI/AMBA and embedded microprocessor verification techniques is a plus

    Occasional travel may be required.

     


    Company Overview

    General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation.  With a global team of 13,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas.  Given the nature of our work and who we are, we value trust, honesty, alignment and transparency.  We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose.  You will also enjoy a flexible work environment where contributions are recognized and rewarded.  If who we are and what we do resonates with you, we invite you to join our high performance team!

     

    General Dynamics is an Equal Opportunity/Affirmative Action Employer that is committed to hiring a diverse and talented workforce.  EOE/Disability/Veteran

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